Neutron-SER Modeling & Simulation for 0.18pm CMOS Technology

نویسندگان

  • Changhong Dai
  • Nagib Hakim
  • Steve Walstra
  • Scott Hareland
  • Jose Maiz
  • Scott Yu
چکیده

This paper presents a new and physical modeling approach for neutron SER with excellent accuracy demonstrated on SRAMs fabricated using 0.18pm CMOS technology. The SER contribution of each type of recoil ion and a fast roll-off behavior of neutron SER for high QCRIT nodes are reported for the first time.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Reducing the Power Consumption in Flash ADC Using 65nm CMOS Technology

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...

متن کامل

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...

متن کامل

Comparative Energy and Delay of Energy Recovery and Square Wave Clock Flip-Flops for High-Performance and Low-Power Applications

Flip-flops are essential elements of a design from both delay and energy aspects. A significant fraction of the total power in highly synchronous systems 1s dissipated over clock networks. Hence, lowpower clocking schemes are promising approaches for future desfgns. Recently, there has been published several energy recovery flip-flops that enable energy recovery from the clock network, resultin...

متن کامل

Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs

Increasing static random access memory (SRAM) bitcell density is a major driving force for semiconductor technology scaling. The industry standard 2x reduction in SRAM bitcell area per technology node has lead to a proliferation in memory intensive applications as greater memory system capacity can be realized per unit area. Coupled with this increasing capacity is an increasing SRAM system-lev...

متن کامل

Logic SER In High-Performance Microprocessors – Myth and Reality

CMOS circuitries are susceptible to soft errors induced by alpha particles or neutron bombardment. The bombardment creates excess carriers in the drain regions of the MOS devices and changes, or temporarily distorts, the voltage values of the charge storage nodes, creating errors in memory arrays or logic elements [1,2,3]. Depending on its criticality, the resulting soft error may or may not le...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2007